Member of Technical Staff, TPU or AMD GPU Performance Engineering

Inferact's mission is to grow vLLM as the world's AI inference engine and accelerate AI progress by making inference cheaper and faster. Founded by the creators and core maintainers of vLLM, we sit at the intersection of models and hardware, a position that took years to build.

About the Role We're looking for an AMD GPU performance engineer to make vLLM a first-class inference engine across the AMD accelerator ecosystem. You'll build and optimize AMD GPU backends, kernels, runtime paths, and benchmarking infrastructure using ROCm, HIP, Triton, CK, AITER, and related tooling so vLLM can deliver frontier inference performance on AMD GPUs.

You’ll work at the boundary of inference systems, kernels, compilers, and hardware architecture, improving performance‑critical paths such as attention, GEMM, sampling, KV cache, and communication‑heavy operations. Your work will help make AMD GPU support in vLLM usable, fast, benchmarked, and maintainable. Skills and

Qualifications Minimum

qualifications: Bachelor's degree or equivalent experience in computer science, engineering, systems, machine learning, or similar. Hands‑on experience optimizing AMD GPU workloads using ROCm, HIP, Triton, CK, AITER, or similar AMD ecosystem tools. Deep understanding of AMD GPU execution, memory behavior, toolchains, kernel performance, and backend‑specific performance constraints.

Experience optimizing ML kernels or inference paths such as attention, GEMM, sampling, KV cache, fused kernels, or communication‑heavy runtime paths. Strong performance profiling and benchmarking skills, with the ability to use measurements, hardware counters, correctness tests, and reproducible benchmarks to guide optimization work. Preferred

qualifications: Experience with vLLM, SGLang, TensorRT‑LLM, ROCm‑based serving, or other LLM inference systems. Familiarity with batching, KV cache, decoding, serving tradeoffs, and backend performance constraints in production inference systems. Experience with compiler and kernel technologies such as Triton, MLIR, LLVM, CK, AITER, HIP, or other kernel DSLs and backend libraries.

Knowledge of quantization methods such as INT8, FP8, mixed precision, or AMD hardware‑specific numeric formats, including accuracy and performance tradeoffs. Bonus points if you have: Contributed to vLLM, ROCm, HIP, Triton, CK, AITER, PyTorch, compiler projects, or other open‑source ML infrastructure. Built AMD GPU benchmarking infrastructure or automated performance regression detection for accelerator workloads.

Worked directly with AMD, accelerator platform teams, or early‑access programs to ship backend, compiler, or inference performance improvements. Logistics Location: This role is based in Singapore. Compensation: Depending on background, skills, and experience, the expected annual salary range for this position is S$200,000 to S$400,000 annually + equity. Visa sponsorship: We sponsor visas on a case‑by‑case basis.

Benefits: Inferact offers a generous

benefits package, including medical, dental, and vision coverage. #J-18808-Ljbffr. Compensation: 0.000000 - 0.000000.